1. Field of the Invention
The present invention relates to a semiconductor device having a contact plug and a method for manufacturing the same and, more particularly, to a conductive layer such as a contact plug for connecting a diffusion layer and wiring.
2. Description of the Related Art
Recent progress of semiconductor techniques has resulted in a trend toward semiconductor devices designed in finer dimensions with a contact hole having a larger aspect ratio. For this reason, techniques that accommodate a contact hole having a large aspect ratio have become important. One of such technique is to fill a contact hole with a contact plug. Such a contact plug must fill a contact hole with preferable step coverage and must further reduce resistance.
A polycrystalline silicon layer added with conductive impurity is frequently used as a material for forming a contact plug of a conventional semiconductor device. For example, this process is carried out as follows. A contact hole is formed in an insulating film so as to extend to reach the source or drain region formed at the surface of a semiconductor substrate of a MOS transistor and, thereafter, a polysilicon film is formed on the entire surface. This polysilicon film is etched back to leave the polysilicon film only in the contact hole. Ion implantation of conductive impurity is carried out and an annealing is performed to diffuse and activate the impurity, thereby completing the contact plug. However, in the case of a contact hole having a large aspect ratio, it has been difficult to dope the contact plug down to the bottom thereof sufficiently by such a process and it has not been easy to provide a contact plug having low resistance.
As a method for solving such a problem, for example, Japanese Patent Application Laid-Open Public No. H4-221821 discloses a method of filling a contact hole having a large aspect ratio with a contact plug which is formed of a layer of a silicon-germanium alloy formed using selective growth.
FIGS. 1A through 1D are sectional views showing steps of the conventional method for manufacturing a semiconductor device disclosed in the above-mentioned patent publication in the order of they are carried out. As shown in FIG. 1A, an n-type diffusion layer 303 is firstly formed at the surface of a p-type silicon substrate 301, and an insulator film 305 is formed so as to cover the entire surface. Anisotropic etching is performed on the insulator film 305 to form a contact hole 307 having a large aspect ratio which reach the n-type diffusion layer 303.
Next, as shown in FIG. 1B, a silicon-germanium alloy layer 356 is formed using a process of selective growth to fill the contact hole 307.
Then, as shown in FIG. 1C, phosphorus ions are implanted in a high dose and an annealing is performed to change the silicon-germanium alloy layer 356 into an n-type silicon-germanium alloy layer 316.
Thereafter, as shown in FIG. 1D, wiring 324 is formed on the surface of the insulator film 305 so as to be directly contacted to the upper surface of the silicon-germanium alloy layer 316.
The resistance of the contact plug disclosed in the above-mentioned patent publication is surely lower than a contact plug formed of polycrystalline silicon. However, for example, when the depth of the junction to the n-type diffusion layer is small, crystalline distortion at the interface between the silicon-germanium alloy layer directly contacted to the diffusion layer and the single crystal silicon substrate is caused because of a mismatch of lattice constants at the interface. By the crystal distortion, an increase in leakage current at the p-n junction is caused.
There is another problem associated with processes for manufacturing a conventions semiconductor device with a silicon substrate. Since the upper surface of the silicon-germanium alloy layer is exposed at the upper end of the contact hole, dissociation of germanium occurs at a photolithography step and the like and this can cause deterioration of the characteristics of a semiconductor device with a silicon substrate. The silicon-germanium alloy layer is not compatible with manufacturing lines for normal semiconductor devices with a silicon substrate.